The instruction set of modern processor units can include a multiple load/store instruction. With a multiple load/store instruction, a single instruction can be used to load or store, for example by reading from or writing to a peripheral block, a plurality of data words.
A processor with a multiple load/store instruction is disclosed in U.S. Pat. No. 6,260,086. For writing a plurality of data words to a serial peripheral interface, a set of peripheral data words is used as well as a first in/first out (FIFO) buffer.
Another example of a processor with a multiple load/store instruction is the ARM Cortex-M0 by ARM Limited.
A feature of known processors with multiple load/store instructions is that the instruction execution is not atomic and may thus be interrupted. When the interrupt processing is finished, the instruction is typically repeated in its entirety. This may have serious consequences. For example, when a multiple store instruction is used to write to a peripheral data interface, a repeat of the entire instruction after an interruption means that the data words which were already written before the interrupt occurred are written twice. This results in incorrect data being written to the peripheral data interface. Likewise, an interruption during a non-atomic multiple load execution can also result in inaccurate data being written.
One way of preventing these effects is to mask interrupts so that they do not interrupt the execution of the multiple load/store instruction. Another way is to simply not use the multiple load/store instruction at all, or at least not when reading from or writing to a peripheral interface. The former way is often not feasible, as the interrupts must be timely handled. The latter way is undesirable, as it leads to more instructions, which increases the overhead of instruction storage, fetching, and decoding.
Therefore, there is a need for a processor circuit and method to use multiple load/store instructions (hereafter also: multiple transfer instruction) which are robust against interruption during execution.
Furthermore, as it is nowadays customary for hardware makers to design-in, for example in a system-on-chip, processor units from third party processor vendors, there is a need for a solution which does not require modifications to the processor unit itself but which can be implemented using circuitry external to the designed-in processor unit.